It is conventional to control the duty cycle of a clock signal for clocking a digital system with a duty cycle correction circuit. For example, double data rate (DDR) transmission uses both the falling edge and the rising edge of a DDR clock signal for data transmission and reception. The data rate for a DDR system is thus twice that as for a single-clock-edge system at the same clocking frequency. Although the use of DDR is thus quite popular, its use faces a number of challenges due to its more stringent timing requirements as compared to single edge data transmission. For example, the DDR clock should have a 50% duty cycle. One can readily appreciate why in that a 50-50 split of the duty cycle for the rising/falling edges of the clock allows the receiver and transmitter the most time possible with each clock edge. As the duty cycle strays from this ideal 50-50 split, one of the clock states has less of each clock cycle than the remaining state. The data eye for the receiver then begins to collapse for the shortened clock state, which leads to undesirable data transmission errors.
Given the importance of obtaining a 50% duty cycle, various duty cycle correcting circuits have been implemented. A conventional duty cycle clock correction circuit 100 is shown in FIG. 1A. A first inverter 105 with a variable pull-up resistance and a variable pull-down resistance inverts an input clock (clk in) to produce a complement output clock signal (clkb out). The core of first inverter 105 is formed by a serial combination of a p-type metal-oxide-semiconductor (PMOS) inverter transistor P1 and an n-type metal-oxide-semiconductor (NMOS inverter transistor M1. If the source of inverter transistor P1 connected directly to a power supply node for a power supply voltage VDD, the pull-up resistance for first inverter 105 would be determined by the on-resistance for inverter transistor P1. To provide a variable pull-up resistance, the source of transistor P1 instead couples to the power supply node through a PMOS pull-up transistor P2 coupled in parallel with a variable-resistance transistor P3 formed as a parallel combination of (N+1) PMOS transistors starting from a zeroth transistor P30 through an Nth transistor P3N, where N is a plural positive integer. An active low enable signal (enb) drives the gate of pull-up transistor P2 so that it is switched on during normal operation for first inverter 105. A first pull-up tuning signal Ctrlbp<0:N> controls which of the transistors P30 through P3N conduct. As more of these transistors conduct, the variable pull-up resistance for first inverter 105 lowers. Conversely, as fewer of the transistors P30 through P3N conduct, the variable pull-up resistance increases. Since pull-up transistor P2 is always on during normal operation, first inverter 105 is powered regardless of the state for the first pull-up tuning signal.
The variable pull-down resistance for first inverter 105 is controlled in an analogous fashion by a first pull-down tuning signal Ctrln<0:N> that controls a variable-resistance transistor M3 formed as a parallel combination of (N+1) NMOS transistors starting from a zeroth transistor M30 through an Nth transistor M3N. These transistors are arranged in parallel with a pull-down NMOS transistor M2 having its gate controlled by an active-high enable signal (en) during normal operation.
A second inverter 110 with a variable pull-up resistance and a variable pull-down resistance inverts a complement input clock signal (clkb in) to form a clock output signal (clk out). The core of second inverter 110 is formed by a serial combination of a PMOS inverter transistor P4 and an NMOS inverter transistor M4. The source of inverter transistor P4 couples to the power supply node through a pull-up PMOS transistor P5 coupled in parallel with a variable-resistance PMOS transistor P6 formed as a parallel combination of (N+1) transistors starting from a zeroth transistor P60 through an Nth transistor P6N. A second pull-up tuning signal ctrlbn<0:1> controls which of the P6 transistors are conducting to control the variable pull-up resistance for second inverter 110. The source of inverter transistor M4 couples to ground through a pull-down NMOS transistor M5 and a variable-resistance NMOS transistor M6 formed as a parallel combination of (N+1) NMOS transistors starting from a zeroth transistor M60 through an Nth transistor M6N. A second pull-down tuning signal Ctrl<0:N> controls which of the transistors M6 are conducting to control the variable pull-down resistance for second inverter 110.
The control of the duty cycle for the clock output signal by duty cycle correction circuit 100 may be better appreciated with reference to the clock waveforms shown in FIG. 1B. The duty cycle for the clock input signal (Clk in) is less than 50%. The complement input clock signal thus has a duty cycle greater than 50%. The variable pull-up resistance for first inverter 105 is thus increased so that a slope for a rising edge for the complement output signal (clkb out) is dampened or slowed. The duty cycle for the complement output signal is thus decreased to equal the desired 50% value. Conversely, the variable pull-down resistance for second inverter 110 is increased so that that a slope for the falling edges for the clock output signal (clk out) is lowered. The duty cycle for the output clock signal is thus increased to equal the desired 50% value.
Although operation of duty cycle correction circuit 100 thus achieves the desired duty cycle correction, note that this correction is only achieved at typical process, voltage, and temperature corners. At more extreme process corners, such as a fast NMOS/slow PMOS corner or a slow NMOS/fast PMOS corner, duty cycle correction circuit 100 cannot obtain the desired duty cycle correction without some duty cycle distortion across the various process corners. Accordingly, there is a need in the art for improved duty cycle correction circuits with reduced duty cycle distortion across a wide range of process, voltage, and temperature variations.